Programmable integrated circuits (ICs) are a well-known type of IC that can be programmed to perform specified logic functions. An exemplary type of programmable IC, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of programmable IC is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable ICs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other programmable ICs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These ICs are known as mask programmable devices. Programmable ICs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “programmable integrated circuit” and “programmable IC” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of programmable IC includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Traditionally, programmable ICs include one or more extensive dedicated clock networks, as well as clock management blocks that provide clock signals for distribution to all portions of the IC via the dedicated clock networks. These clock management blocks can be quite complicated, encompassing, for example, digital locked loops (DLLs), phase locked loops (PLLs), digital clock managers (DCMs), and so forth. For example, the Virtex®-4 series of FPGAs from Xilinx, Inc. includes up to 20 DCMs, each providing individual clock deskewing, frequency synthesis, phase shifting, and/or dynamic reconfiguration for a portion of the IC. Thus, a significant amount of design and testing time is required to provide these features in the device, and their use also requires time and effort on the part of the system designer. Additionally, because a global clock signal may be needed at virtually any position in a programmable IC, a global clock network is very extensive and consumes large amounts of power when in use.
A large IC design typically includes a large number of “race conditions”, where two or more signals are “racing” each other to a given destination, such as the input terminals of a logic block. Typically one of these signals is a clock signal, which must reach the destination within a certain window within which the data being provided to the destination is valid. Thus, the well-known timing requirements known as the “setup time” for data (the amount of time by which the data signal must precede the active edge of the clock signal at the input terminals of the logic block) and the “hold time” for the data (the amount of time the data signal must remain at the data input terminal after the arrival of the active edge of the clock signal) are vital to the success of a clocked design, and must be met for every clocked element, or the logic cannot be expected to operate properly.
One of the biggest challenges in providing clock services for a large programmable IC is the problem of skew. Clock and data signals distributed over a large area are naturally delayed by varying amounts, depending upon their origins and destinations as well as the nature of the network paths through which they are distributed. Therefore, clock signals are often skewed one from another, and from the related data signals. Yet, the setup and hold time requirements must be met in every instance to guarantee reliable operation of a user design implemented in the programmable IC. Therefore, it is clear that the design of reliable clock networks for a programmable IC containing potentially a hundred thousand flip-flops or other clock elements may consume a large amount of engineering resources and may adversely impact the design cycle of the programmable IC.